Dummy metal bonding pads for underfill application in semiconductor die packaging and methods of forming the same

ABSTRACT

A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.

BACKGROUND

Interfaces between a fan-out wafer level package (FOWLP) and a moldingcompound material portion are subjected to mechanical stress duringsubsequent handling of an assembly of the FOWLP, the underfill materialportion, and a packaging substrate, such as attachment of the packagingsubstrate to a printed circuit board (PCB). In addition, interfacesbetween a FOWLP and an underfill material portion are subjected tomechanical stress during use within a computing device, such as when theFOWLP heats up during usage and mismatch in thermal expansion ofcomponents of the FOWLP induces thermal stress or when a mobile deviceis accidently dropped to cause a mechanical shock during usage. Cracksmay be formed in the underfill material, and may induce additionalcracks in a semiconductor die, solder material portions, redistributionstructures, and/or various dielectric layers within a semiconductor dieor within a package substrate. Thus, formation of cracks in theunderfill material needs to be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a vertical cross-sectional view of a region of an exemplarystructure that includes a first carrier substrate and redistributionstructures according to an embodiment of the present disclosure.

FIG. 2A is vertical cross-sectional view of a region of the exemplarystructure after formation of redistribution-side bonding structures andfirst solder material portions according to an embodiment of the presentdisclosure.

FIG. 2B is a top-down view of the region of the exemplary structure ofFIG. 2A.

FIG. 3A is a vertical cross-sectional view of a region the exemplarystructure after attaching semiconductor dies according to an embodimentof the present disclosure.

FIG. 3B is a top-down view of the region of the exemplary structure ofFIG. 3A.

FIG. 4A is a top-down view of a region of a first alternativeconfiguration of the exemplary structure after attaching semiconductordies according to an embodiment of the present disclosure.

FIG. 4B is a top-down view of a region of a second alternativeconfiguration of the exemplary structure after attaching semiconductordies according to an embodiment of the present disclosure.

FIG. 4C is a top-down view of a region of a third alternativeconfiguration of the exemplary structure after attaching semiconductordies according to an embodiment of the present disclosure.

FIG. 5A illustrate top-down views of alternative shapes for the firstsolder material portions according to an embodiment of the presentdisclosure.

FIG. 5B illustrate top-down views of additional alternative shapes forthe first solder material portions according to an embodiment of thepresent disclosure.

FIG. 6 is a magnified vertical cross-sectional view of a high bandwidthmemory die.

FIG. 7A is a vertical cross-sectional view of a region of the exemplarystructure after formation of first underfill material portions accordingto an embodiment of the present disclosure.

FIG. 7B is a top-down view of the region of the exemplary structure ofFIG. 7A.

FIG. 8A is a vertical cross-sectional view of a region of the exemplarystructure after formation of an epoxy molding compound (EMC) matrixaccording to an embodiment of the present disclosure.

FIG. 8B is a top-down view of the region of the exemplary structure ofFIG. 8A.

FIG. 9 is a vertical cross-sectional view of a region of the exemplarystructure after attaching a second carrier substrate and detaching thefirst carrier substrate according to an embodiment of the presentdisclosure.

FIG. 10 is a vertical cross-sectional view of a region of the exemplarystructure after formation of fan-out bonding pads according to anembodiment of the present disclosure.

FIG. 11 is a vertical cross-sectional view of a region of the exemplarystructure after detaching the second carrier substrate according to anembodiment of the present disclosure.

FIG. 12 is a vertical cross-sectional view of a region of the exemplarystructure during dicing of a reconstituted wafer and the EMC matrixaccording to an embodiment of the present disclosure.

FIG. 13 is a vertical cross-sectional view of a fan-out packageaccording to an embodiment of the present disclosure.

FIG. 14 is a vertical cross-sectional view of an exemplary structureafter attaching the fan-out package to a package substrate according toan embodiment of the present disclosure.

FIG. 15 is a vertical cross-sectional view of the exemplary structureafter formation of a second underfill material portion according to anembodiment of the present disclosure.

FIG. 16 is a vertical cross-sectional view of the exemplary structureafter the package substrate is attached to a printed circuit board (PCB)according to an embodiment of the present disclosure.

FIG. 17 is a flowchart illustrating steps for forming an exemplarystructure according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. Unless explicitly statedotherwise, each element having the same reference numeral is presumed tohave the same material composition and to have a thickness within a samethickness range.

The present disclosure is directed to semiconductor devices, andparticularly to uniform application of an underfill material insemiconductor die packaging. Generally, the methods and structures ofthe present disclosure may be used to provide a chip package structuresuch as a fan-out wafer level package (FOWLP) or a fan-out panel levelpackage (FOPLP). While the present disclosure is described using anFOWLP configuration, the methods and structures of the presentdisclosure may be implemented in an FOPLP configuration or any otherfan-out or fan-in package configuration.

Metal bonding structures on semiconductor dies and redistributionstructures may increase the capillary force during application of anunderfill material. The increased capillary force may be advantageouslyused to enhance uniformity of the underfill material distribution aroundthe metal bonding structures in a die-to-die gap or in a die-to-packagegap (such as a die-to-chip-scale-package gap). According to an aspect ofthe present disclosure, the flow uniformity of an underfill material maybe enhanced using dummy metal bonding structures and/or dummy soldermaterial portions. Void formation within an underfill material portionwithin a die-to-die gap or a die-to-package gap may be avoided orreduced through use of the dummy structures of the present disclosurethat enhance the capillary force in inter-die regions.

For example, a high performance computing (HPC) package may comprisemultiple semiconductor dies including at least one system-on-chip (SoC)die and at least one high bandwidth memory (HBM) die within a chiplet,such as a fan-out wafer level package. Die-to-die gaps and/ordie-to-chip-scale-package gaps increase the complexity of an underfillmaterial dispensation step. In instances in which the underfill materialflows non-uniformly, voids may be formed within the underfill materialportion in gap regions. Such voids in the underfill material may causesolder bridging or a “popcorn” phenomenon in which solder materialportions are securely attached to metal bonding structures. The dummystructures of embodiments of the present disclosure may be used to avoidor reduce formation voids in the underfill material. The various aspectsand embodiments of the methods and structures of the present disclosureare described with reference to accompanying drawings.

Referring to FIG. 1 , an exemplary structure according to an embodimentof the present disclosure includes a first carrier substrate 300 andredistribution structures 920 formed on a front side surface of thefirst carrier substrate 300. The first carrier substrate 300 may includean optically transparent substrate such as a glass substrate or asapphire substrate. The diameter of the first carrier substrate 300 maybe in a range from 150 mm to 290 mm, and the thickness of the firstcarrier substrate 300 may be in a range from 500 microns to 2,000microns, although lesser and greater thicknesses may also be used.Alternatively, the first carrier substrate 300 may be provided in arectangular panel format.

A first adhesive layer 301 may be applied to the front-side surface ofthe first carrier substrate 300. In one embodiment, the first adhesivelayer 301 may be a light-to-heat conversion (LTHC) layer. The LTHC layermay be a solvent-based coating applied using a spin coating method. TheLTHC layer may convert ultraviolet light to heat, which may cause thematerial of the LTHC layer to lose adhesion. Alternatively, the firstadhesive layer 301 may include a thermally decomposing adhesivematerial. For example, the first adhesive layer 301 may include anacrylic pressure-sensitive adhesive that decomposes at an elevatedtemperature. The debonding temperature of the thermally decomposingadhesive material may be in a range from 150 degrees to 200 degreesCelsius.

Redistribution structures 920 may be formed over the first adhesivelayer 301. Specifically, a redistribution structure 920 may be formedwithin each unit area UA, which is the area of a repetition unit that isrepeated in a two-dimensional array over the first carrier substrate300. Each redistribution structure 920 may include redistributiondielectric layers 922 and redistribution wiring interconnects 924. Theredistribution dielectric layers 922 include a respective dielectricpolymer material such as polyimide (PI), benzocyclobutene (BCB), orpolybenzobisoxazole (PBO). Other suitable materials may be within thecontemplated scope of disclosure. Each redistribution dielectric layer922 may be formed by spin coating and drying of the respectivedielectric polymer material. The thickness of each redistributiondielectric layer 922 may be in a range from 2 microns to 40 microns,such as from 4 microns to 20 microns. Each redistribution dielectriclayer 922 may be patterned, for example, by applying and patterning arespective photoresist layer thereabove, and by transferring the patternin the photoresist layer into the redistribution dielectric layer 922using an etch process such as an anisotropic etch process. Thephotoresist layer may be subsequently removed, for example, by ashing.

Each of the redistribution wiring interconnects 924 may be formed bydepositing a metallic seed layer by sputtering, by applying andpatterning a photoresist layer over the metallic seed layer to form apattern of openings through the photoresist layer, by electroplating ametallic fill material (such as copper, nickel, or a stack of copper andnickel), by removing the photoresist layer (for example, by ashing), andby etching portions of the metallic seed layer located between theelectroplated metallic fill material portions. The metallic seed layermay include, for example, a stack of a titanium barrier layer and acopper seed layer. The titanium barrier layer may have thickness in arange from 50 nm to 400 nm, and the copper seed layer may have athickness in a range from 100 nm to 500 nm. The metallic fill materialfor the redistribution wiring interconnects 924 may include copper,nickel, or copper and nickel. The thickness of the metallic fillmaterial that is deposited for each redistribution wiring interconnect924 may be in a range from 2 microns to 40 microns, such as from 4microns to 10 microns, although lesser or greater thicknesses may alsobe used. The total number of levels of wiring in each redistributionstructure 920 (i.e., the levels of the redistribution wiringinterconnects 924) may be in a range from 1 to 10. Other suitablematerials are within the contemplated scope of disclosure. A periodictwo-dimensional array (such as a rectangular array) of redistributionstructures 920 may be formed over the first carrier substrate 300. Thelayer including all redistribution structures 920 is herein referred toas a redistribution structure layer. The redistribution structure layerincludes a two-dimensional array of redistribution structures 920.

Referring to FIGS. 2A and 2B, at least one metallic material and a firstmaterial may be sequentially deposited over the front-side surface ofthe redistribution structures 920. The at least one metallic materialcomprises a material that may be used for metallic bumps, such ascopper. The thickness of the at least one metallic material may be in arange from 5 microns to 60 microns, such as from 10 microns to 30microns, although lesser and greater thicknesses may also be used. Thefirst material may comprise a first material suitable for C2 bonding,i.e., for microbump bonding. The thickness of the first material may bein a range from 2 microns to 30 microns, such as from 4 microns to 15microns, although lesser and greater thicknesses may also be used.

The first material and the at least one metallic material may bepatterned into discrete arrays of first solder material portions 940 andarrays of metal bonding structures, which are herein referred to asarrays of redistribution-side bonding structures 938. Each array ofredistribution-side bonding structures 938 is formed within a respectiveunit area UA. Each array of first solder material portions 940 is formedwithin a respective unit area UA. Each first solder material portion 940may have a same horizontal cross-sectional shape as an underlyingredistribution-side bonding structures 938.

In one embodiment, the redistribution-side bonding structures 938 mayinclude, and/or may consist essentially of, copper or acopper-containing alloy. Other suitable materials are within thecontemplated scope of disclosure. The thickness of theredistribution-side bonding structures 938 may be in a range from 5microns to 60 microns, although lesser or greater thicknesses may alsobe used. The redistribution-side bonding structures 938 may havehorizontal cross-sectional shapes of rectangles, rounded rectangles,circles, regular polygons, irregular polygons, or any othertwo-dimensional curvilinear shape having a closed periphery. In oneembodiment, redistribution-side bonding structures 938 may be configuredfor microbump bonding (i.e., C2 bonding), and may have a thickness in arange from 10 microns to 30 microns, although lesser or greaterthicknesses may also be used. In this embodiment, each array ofredistribution-side bonding structures 938 may be formed as an array ofmicrobumps (such as copper pillars) having a lateral dimension in arange from 10 microns to 25 microns, and having a pitch in a range from20 microns to 50 microns.

Referring to FIGS. 3A and 3B, a set of at least one semiconductor die(700, 800) may be bonded to each redistribution structure 920. In oneembodiment, the redistribution structures 920 may be arranged as atwo-dimensional periodic array, and multiple sets of at least onesemiconductor die (700, 800) may be bonded to the redistributionstructures 920 as a two-dimensional periodic rectangular array of setsof the at least one semiconductor die (700, 800). Each set of at leastone semiconductor die (700, 800) includes at least one semiconductordie. Each set of at least one semiconductor die (700, 800) may includeany set of at least one semiconductor die known in the art. In oneembodiment, each set of at least one semiconductor die (700, 800) maycomprise a plurality of semiconductor dies (700, 800). For example, eachset of at least one semiconductor die (700, 800) may include at leastone system-on-chip (SoC) die 700 and/or at least one memory die 800.Each SoC die 700 may comprise an application processor die, a centralprocessing unit die, or a graphic processing unit die. In oneembodiment, the at least one memory die 800 may comprise a highbandwidth memory (HBM) die that includes a vertical stack of staticrandom access memory dies. In one embodiment, the at least onesemiconductor die (700, 800) may include at least one system-on-chip(SoC) die and a high bandwidth memory (HBM) die including a verticalstack of static random access memory (SRAM) dies that are interconnectedto one another through microbumps and are laterally surrounded by anepoxy molding material enclosure frame.

Referring to FIGS. 3A and 3C, each of the semiconductor dies (700, 800)may include a respective array of die-side bonding structures (780,880). For example, each SoC die 700 may include an array of SoC metalbonding structures 780, and each memory die 800 may include an array ofmemory-die metal bonding structures 880. Each of the semiconductor dies(700, 800) may be positioned in a face-down position such that die-sidebonding structures (780, 880) face the first solder material portions940. Each set of a plurality of semiconductor dies (700, 800) may beplaced within a respective unit area UA. Placement of the semiconductordies (700, 800) may be performed using a pick and place apparatus sothat each of the die-side bonding structures (780, 880) is placed on atop surface of a respective one of the first solder material portions940.

Generally, a redistribution structure 920 including redistribution-sidebonding structures 938 thereupon may be provided, and a plurality ofsemiconductor dies (700, 800) including a respective set of die-sidebonding structures (780, 880) may be provided. The plurality ofsemiconductor dies (700, 800) may be bonded to the redistributionstructure 920 using first solder material portions 940 that are bondedto a respective redistribution-side bonding structure 938 within a firstsubset of the redistribution-side bonding structures 938 and to arespective one of the die-side bonding structures (780, 880). A secondsubset of the redistribution-side bonding structures 938 is not bondedto any of the plurality of semiconductor dies (700, 800).

The first subset of the redistribution-side bonding structures 938 maybe bonded to a first subset of the first solder material portions 940,and the second subset of the redistribution-side bonding structures 938may be bonded to a second subset of the first solder material portions940. The second subset of the redistribution-side bonding structures 938is herein referred to as dummy redistribution-side bonding structures938D. The second subset of the first solder material portions 940 isherein referred to as dummy solder material portions 940D. The secondsubset of the redistribution-side bonding structures 938 (including thedummy redistribution-side bonding structure 938D) is devoid of any bondsto any of the die-side bonding structures (780, 880) of the plurality ofsemiconductor dies (700, 800). Put another way, the second subset of theredistribution-side bonding structures 938 (including the dummyredistribution-side bonding structure 938D) is not bonded to any of thedie-side bonding structures (780, 880) of the plurality of semiconductordies (700, 800).

Each redistribution-side bonding structure 938 within the first subsetof the redistribution-side bonding structures 938 may have an arealoverlap with a respective one of the plurality of semiconductor dies(700, 800) in a plan view (such as a top-down view), and may be locatedentirety within the area of the respective one of the plurality ofsemiconductor dies (700, 800) in the plan view. Each dummyredistribution-side bonding structure 938D does not have any arealoverlap with the plurality of semiconductor dies (700, 800) in the planview, and may be located entirety between areas of a neighboring pair ofsemiconductor dies (700, 800) within the plurality of semiconductor dies(700, 800) in the plan view.

Each first solder material portion 940 within the first subset of thefirst solder material portions 940 may have an areal overlap with arespective one of the plurality of semiconductor dies (700, 800) in theplan view, and may be located entirety within the area of the respectiveone of the plurality of semiconductor dies (700, 800) in the plan view.Each dummy solder material portion 940D does not have any areal overlapwith the plurality of semiconductor dies (700, 800) in the plan view,and may be located entirety between areas of a neighboring pair ofsemiconductor dies (700, 800) within the plurality of semiconductor dies(700, 800) in the plan view.

Generally, first solder material portions 940 (such as the first subsetof the first solder material portions 940) may be formed on the firstsubset of the redistribution-side bonding structures 938, and additionalfirst solder material portions 940 (such as the dummy solder materialportions 940D) may be formed on the second subset of theredistribution-side bonding structures 938 (i.e., on the dummyredistribution-side bonding structures 938D). The additional firstsolder material portions (such as the dummy solder material portions940D) are not bonded to any of the die-side bonding structures (780,880). The additional first solder material portions (such as the dummysolder material portions 940D) are devoid of any bonds to any of thedie-side bonding structures (780, 880).

In one embodiment, the dummy solder material portions 940D may belocated on a respective dummy redistribution-side bonding structure 938Dselected from the second subset of the redistribution-side bondingstructures 938, and do not contact any of the plurality of semiconductordies (700, 800). In one embodiment, the dummy solder material portions940D comprises at least one row of dummy solder material portions 940Darranged along a direction that is parallel to, and is located between,a pair of sidewalls of a neighboring pair of semiconductor dies (700,800) selected from the plurality of semiconductor dies (700, 800). Eachof the dummy solder material portions 940D has a same materialcomposition as the sets of solder material portions 940 that are bondedto a respective pair of a redistribution-side bonding structure 938 anda die-side bonding structure (780, 880).

Generally, the dummy redistribution-side bonding structures 938D and thedummy solder material portions 940D do not have any areal overlap withthe plurality of semiconductor dies (700, 800) in the plan view (such asthe top-down view of FIG. 3B) within each unit area UA. In oneembodiment, a row of dummy redistribution-side bonding structures 938Dand a row of dummy solder material portions 940D may be located betweenareas of a neighboring pair of semiconductor dies (700, 800) within theplurality of semiconductor dies (700, 800) in the plan view. Thearrangement of the dummy redistribution-side bonding structures 938D andthe dummy solder material portions 940D may vary depending on thearrangement of the plurality of semiconductor dies (700, 800) withineach unit area UA.

FIGS. 4A-4C illustrate alternative configurations of the exemplarystructure that may be derived from the exemplary structure of FIGS. 3Aand 3B by varying the arrangement of the semiconductor dies (700, 800)and/or the total number of semiconductor dies (700, 800) and/or thetype(s) of the semiconductor dies (700, 800). The semiconductor dies(701, 702, 703, 704) within the alternative configurations of theexemplary structure in FIGS. 4A-4C include a first semiconductor die701, a second semiconductor die 702, and optionally a thirdsemiconductor die 703 and/or a fourth semiconductor die 704. Each of thesemiconductor dies (701, 702, 703, 704) may comprise an SoC die 700 or amemory die 800. The pattern of the dummy redistribution-side bondingstructures 938D and the dummy solder material portions 940D may includea single-row pattern illustrated in FIG. 4A, a multiple-row patternillustrated in FIG. 4B, and/or a cross pattern illustrated in FIG. 4C.Generally, any pattern may be used for arrangement of the dummyredistribution-side bonding structures 938D and the dummy soldermaterial portions 940D provided that at least one dummyredistribution-side bonding structure 938 and at least one dummy soldermaterial portion 940D is placed between a neighboring pair ofsemiconductor dies {(700, 800) or (701, 702, 703, 704).

While FIGS. 3A, 3B, and 4A-4C illustrate configurations in which thedummy solder material portions 940D and the dummy redistribution-sidebonding structures 938D have horizontal cross-sectional shapes of arespective rectangle. Generally, the dummy solder material portions 940Dand the dummy redistribution-side bonding structures 938D may have ahorizontal cross-sectional shape of any two-dimensional curvilinearshape having a closed periphery.

Referring to FIG. 5A, alternative shapes for the dummy solder materialportions 940D (and for the dummy redistribution-side bonding structures938) are shown, which may comprise a regular polygon having equal sides.

Referring to FIG. 5B, additional alternative shapes for the dummy soldermaterial portions 940D (and for the dummy redistribution-side bondingstructures 938) are shown, which may comprise an irregular polygon.

Yet alternatively, the dummy solder material portions 940D (and for thedummy redistribution-side bonding structures 938) may have horizontalcross-sectional shapes of a circle, an ellipse, an oval, or a curvedtwo-dimensional shape having a closed periphery.

Referring to FIG. 6 , a high bandwidth memory (HBM) die 810 isillustrated, which may be used as a memory die 800 within the exemplarystructures of FIGS. 3A and 3B, 4A, 4B, and/or 4C. The HBM die 810includes a vertical stack of static random access memory dies (811, 812,813, 814, 815) that are interconnected to one another through microbumps820 and are laterally surrounded by an epoxy molding material enclosureframe 816. The gaps between vertically neighboring pairs of the randomaccess memory dies (811, 812, 813, 814, 815) may be filled with a HBMunderfill material portions 822 that laterally surrounds a respectiveset of microbumps 820. The HBM die 810 may comprise an array ofmemory-die metal bonding structures 880 configured to be bonded to asubset of an array of redistribution-side bonding structures 938 withina unit area UA. The HBM die 810 may be configured to provide a highbandwidth as defined under JEDEC standards, i.e., standards defined byThe JEDEC Solid State Technology Association.

Referring to FIGS. 7A and 7B, a first underfill material may be appliedinto each gap between the redistribution structures 920 and sets of aplurality of semiconductor dies (700, 800) that are bonded to theredistribution structures 920. The first underfill material may compriseany underfill material known in the art. A first underfill materialportion 950 may be formed within each unit area UA between aredistribution structure 920 and an overlying set of a plurality ofsemiconductor dies (700, 800). The first underfill material portions 950may be formed by injecting the first underfill material around arespective array of first solder material portions 940 in a respectiveunit area UA. Any known underfill material application method may beused, which may be, for example, the capillary underfill method, themolded underfill method, or the printed underfill method.

Within each unit area UA, a first underfill material portion 950laterally surrounds, and contacts, each of the first solder materialportions 940 within the unit area UA, which include a first subset ofthe first solder material portions 940 that may be bonded to arespective pair of a redistribution-side bonding structure 938 and adie-side bonding structure (780 or 880), and a second subset of thefirst solder material portions 940 (i.e., the dummy solder materialportions 940D) that are not bonded to any of the die-side bondingstructures (780 or 880). The first underfill material portion 950 may beformed around, and may contact, the first solder material portions 940,the redistribution-side bonding structures 938, and the die-side bondingstructures (780, 880) in the unit area UA. Within each unit area UA, thedummy redistribution-side bonding structures 938D (i.e., the subset ofthe redistribution-side bonding structures 938 that is not bonded (i.e.,devoid of any bonds) to any of the die-side bonding structures (780,880) of the plurality of semiconductor dies (700, 800), may be laterallysurrounded by, and may contact, the first underfill material portion950.

Each redistribution structure 920 in a unit area UA may includeredistribution-side bonding structures 938. A plurality of semiconductordies (700, 800) comprising a respective set of die-side bondingstructures (780, 880) may be attached to a respective subset of theredistribution-side bonding structures 938 through a respective set offirst solder material portions 940 (which include the first subset ofthe first solder material portions 940). Within each unit area UA, afirst underfill material portion 950 laterally surrounds theredistribution-side bonding structures 938 and the die-side bondingstructures (780, 880) of the plurality of semiconductor dies (700, 800).A subset of the redistribution-side bonding structures 938 (i.e., thedummy redistribution-side bonding structures 938D) is not bonded to anyof the die-side bonding structures (780, 880) of the plurality ofsemiconductor dies (700, 800), and may be laterally surrounded by thefirst underfill material portion 950.

Referring to FIGS. 8A and 8B, an epoxy molding compound (EMC) may beapplied to the gaps between contiguous assemblies of a respective set ofsemiconductor dies (700, 800) and a first underfill material portion950. The EMC may include an epoxy-containing compound that may behardened (i.e., cured) to provide a dielectric material portion havingsufficient stiffness and mechanical strength. The EMC may include epoxyresin, hardener, silica (as a filler material), and other additives. TheEMC may be provided in a liquid form or in a solid form depending on theviscosity and flowability. Liquid EMC provides better handling, goodflowability, less voids, better fill, and less flow marks. Solid EMCprovides less cure shrinkage, better stand-off, and less die drift. Ahigh filler content (such as 85% in weight) within an EMC may shortenthe time in mold, lower the mold shrinkage, and reduce the mold warpage.Uniform filler size distribution in the EMC may reduce flow marks, andmay enhance flow ability. The curing temperature of the EMC may be lowerthan the release (debonding) temperature of the first adhesive layer 301if the adhesive layer includes a thermally debonding material. Forexample, the curing temperature of the EMC may be in a range from 125°C. to 150° C.

The EMC may be cured at a curing temperature to form an EMC matrix 910Mthat laterally surrounds and embeds each assembly of a set ofsemiconductor dies (700, 800) and a first underfill material portion950. The EMC matrix 910M may include a plurality of epoxy moldingcompound (EMC) die frames that may be laterally adjoined to one another.Each EMC die frame may be a portion of the EMC matrix 910M that islocated within a respective unit area UA. Thus, each EMC die frame maylaterally surround and embed a respective a set of semiconductor dies(700, 800) and a respective first underfill material portion 950.

Portions of the EMC matrix 910M that overlies the horizontal planeincluding the top surfaces of the semiconductor dies (700, 800) may beremoved by a planarization process. For example, the portions of the EMCmatrix 910M that overlies the horizontal plane may be removed using achemical mechanical planarization. The combination of the remainingportion of the EMC matrix 910M, the semiconductor dies (700, 800), thefirst underfill material portions 950, and the two-dimensional array ofredistribution structures 920 comprises a reconstituted wafer 900W. Eachportion of the EMC matrix 910M located within a unit area UA constitutesan EMC die frame.

Referring to FIG. 9 , a second adhesive layer 401 may be applied to thephysically exposed planar surface of the reconstituted wafer 900W, i.e.,the physically exposed surfaces of the EMC matrix 910M, thesemiconductor dies (700, 800), and the first underfill material portions950. In one embodiment, the second adhesive layer 401 may comprise asame material as, or may comprise a different material from, thematerial of the first adhesive layer 301. If the first adhesive layer301 comprises a thermally decomposing adhesive material, the secondadhesive layer 401 comprises another thermally decomposing adhesivematerial that decomposes at a higher temperature, or may comprise alight-to-heat conversion material.

A second carrier substrate 400 may be attached to the second adhesivelayer 401. The second carrier substrate 400 may be attached to theopposite side of the reconstituted wafer 900W relative to the firstcarrier substrate 300. Generally, the second carrier substrate 400 maycomprise any material that may be used for the first carrier substrate300. The thickness of the second carrier substrate 400 may be in a rangefrom 500 microns to 2,000 microns, although lesser and greaterthicknesses may also be used.

The first adhesive layer 301 may be decomposed by ultraviolet radiationor by a thermal anneal at a debonding temperature. In embodiments inwhich the first carrier substrate 300 includes an optically transparentmaterial and the first adhesive layer 301 includes an LTHC layer, thefirst adhesive layer 301 may be decomposed by irradiating ultravioletlight through the transparent carrier substrate. The LTHC layer may beabsorb the ultraviolet radiation and generate heat, which decomposes thematerial of the LTHC layer and cause the transparent first carriersubstrate 300 to be detached from the reconstituted wafer 900W. Inembodiments in which the first adhesive layer 301 includes a thermallydecomposing adhesive material, a thermal anneal process at a debondingtemperature may be performed to detach the first carrier substrate 300from the reconstituted wafer 900W.

Referring to FIG. 10 , fan-out bonding pads 928 and second soldermaterial portions 290 may be formed by depositing and patterning a stackof at least one metallic material that may function as metallic bumpsand a solder material layer. The metallic fill material for the fan-outbonding pads 928 may include copper. Other suitable materials are withinthe contemplated scope of disclosure. The thickness of the fan-outbonding pads 928 may be in a range from 5 microns to 100 microns,although lesser or greater thicknesses may also be used. The fan-outbonding pads 928 and the second solder material portions 290 may havehorizontal cross-sectional shapes of rectangles, rounded rectangles, orcircles. Other suitable shapes are within the contemplated scope ofdisclosure. In embodiments in which the fan-out bonding pads 928 areformed as C4 (controlled collapse chip connection) pads, the thicknessof the fan-out bonding pads 928 may be in a range from 5 microns to 50microns, although lesser or greater thicknesses may also be used. Insome embodiments, the fan-out bonding pads 928 may be, or include, underbump metallurgy (UBM) structures. The configurations of the fan-outbonding pads 928 are not limited to be fan-out structures.Alternatively, the fan-out bonding pads 928 may be configured formicrobump bonding (i.e., C2 bonding), and may have a thickness in arange from 30 microns to 100 microns, although lesser or greaterthicknesses may also be used. In such an embodiment, the fan-out bondingpads 928 may be formed as an array of microbumps (such as copperpillars) having a lateral dimension in a range from 10 microns to 25microns, and having a pitch in a range from 20 microns to 50 microns. Insome embodiments, the second solder material portions 290 may be, orinclude, copper pillars.

The fan-out bonding pads 928 and the second solder material portions 290may be formed on the opposite side of the EMC matrix 910M and thetwo-dimensional array of sets of semiconductor dies (700, 800) relativeto the redistribution structure layer. The redistribution structurelayer includes a three-dimensional array of redistribution structures920. Each redistribution structure 920 may be located within arespective unit area UA. Each redistribution structure 920 may compriseredistribution dielectric layers 922, redistribution wiringinterconnects 924 embedded in the redistribution dielectric layers 922,and fan-out bonding pads 928. The fan-out bonding pads 928 may belocated on an opposite side of the redistribution-side bondingstructures 938 relative to the redistribution dielectric layers 922, andmay be electrically connected to a respective one of theredistribution-side bonding structures 938.

Referring to FIG. 11 , the second adhesive layer 401 may be decomposedby ultraviolet radiation or by a thermal anneal at a debondingtemperature. In embodiments in which the second carrier substrate 400includes an optically transparent material and the second adhesive layer401 includes an LTHC layer, the second adhesive layer 401 may bedecomposed by irradiating ultraviolet light through the transparentcarrier substrate. In embodiments in which the second adhesive layer 401includes a thermally decomposing adhesive material, a thermal annealprocess at a debonding temperature may be performed to detach the secondcarrier substrate 400 from the reconstituted wafer 900W.

Referring to FIG. 12 , the reconstituted wafer 900W including thefan-out bonding pads 928 may be subsequently diced along dicing channelsby performing a dicing process. The dicing channels correspond to theboundaries between neighboring pairs of die areas DA. Each diced unitfrom the reconstituted wafer 900W comprises a fan-out package 900. Inother words, each diced portion of the assembly of the two-dimensionalarray of sets of semiconductor dies (700, 800), the two-dimensionalarray of first underfill material portions 950, the EMC matrix 910M, andthe two-dimensional array of redistribution structures 920 constitutes afan-out package 900. Each diced portion of the EMC matrix 910Mconstitutes a molding compound die frame 910. Each diced portion of theredistribution structure layer (which includes the two-dimensional arrayof redistribution structures 920) constitutes a redistribution structure920.

Referring to FIG. 13 , a fan-out package 900 obtained by dicing theexemplary structure at the processing steps of FIG. 12 is illustrated.The fan-out package 900 comprises a redistribution structure 920including redistribution-side bonding structures 938, a plurality ofsemiconductor dies (700, 800) comprising a respective set of die-sidebonding structures (780, 880) that is attached to a respective subset ofthe redistribution-side bonding structures 938 through a respective setof first solder material portions 940, a first underfill materialportion 950 laterally surrounding the redistribution-side bondingstructures 938 and the die-side bonding structures (780, 880) of theplurality of semiconductor dies (700, 800), wherein a subset of theredistribution-side bonding structures 938 is located between aneighboring pair of semiconductor dies (700, 800) selected from theplurality of semiconductor dies (700, 800) in a plan view, i.e., a viewalong a direction that is perpendicular to an interface between theredistribution structure 920 and the first underfill material portion950. The fan-out package 900 may comprise a molding compound die frame910 laterally surrounding the plurality of semiconductor dies (700, 800)and comprising a molding compound material. In one embodiment, themolding compound die frame 910 may include sidewalls that are verticallycoincident with sidewalls of the redistribution structure 920, i.e.,located within same vertical planes as the sidewalls of theredistribution structure 920. Generally, the molding compound die frame910 may be formed around the plurality of semiconductor dies (700, 800)after formation of the first underfill material portion 950 within eachfan-out package 900. The molding compound material contacts a peripheralportion of a planar surface of the redistribution structure 920.

Referring to FIG. 14 , a package substrate 200 may be bonded to thefan-out package 900 through the second solder material portions 290. Thepackage substrate 200 may be a cored package substrate including a coresubstrate 210, or a coreless package substrate that does not include apackage core. Alternatively, the package substrate 200 may include asystem-on-integrated package substrate (SoIS) including redistributionlayers and/or dielectric interlayers, at least one embedded interposer(such as a silicon interposer). Such a system-integrated packagesubstrate may include layer-to-layer interconnections using soldermaterial portions, microbumps, underfill material portions (such asmolded underfill material portions), and/or an adhesion film. While thepresent disclosure is described using an exemplary substrate package, itis understood that the scope of the present disclosure is not limited byany particular type of substrate package and may include an SoIS. Thecore substrate 210 may include a glass epoxy plate including an array ofthrough-plate holes. An array of through-core via structures 214including a metallic material may be provided in the through-plateholes. Each through-core via structure 214 may, or may not, include acylindrical hollow therein. Optionally, dielectric liners 212 may beused to electrically isolate the through-core via structures 214 fromthe core substrate 210.

The package substrate 200 may include board-side surface laminar circuit(SLC) 240 and a chip-side surface laminar circuit (SLC) 260. Theboard-side SLC may include board-side insulating layers 242 embeddingboard-side wiring interconnects 244. The chip-side SLC 260 may includechip-side insulating layers 262 embedding chip-side wiring interconnects264. The board-side insulating layers 242 and the chip-side insulatinglayers 262 may include a photosensitive epoxy material that may belithographically patterned and subsequently cured. The board-side wiringinterconnects 244 and the chip-side wiring interconnects 264 may includecopper that may be deposited by electroplating within patterns in theboard-side insulating layers 242 or the chip-side insulating layers 262.

In one embodiment, the package substrate 200 includes a chip-sidesurface laminar circuit 260 comprising chip-side wiring interconnects264 connected to an array of chip-side bonding pads 268 that is bondedto the array of second solder material portions 290, and a board-sidesurface laminar circuit 240 including board-side wiring interconnects244 connected to an array of board-side bonding pads 248. The array ofboard-side bonding pads 248 is configured to allow bonding throughsolder balls. The array of chip-side bonding pads 268 is configured toallow bonding through C4 solder balls. Generally, any type of packagesubstrate 200 may be used. While the present disclosure is describedusing an embodiment in which the package substrate 200 includes achip-side surface laminar circuit 260 and a board-side surface laminarcircuit 240, embodiments are expressly contemplated herein in which oneof the chip-side surface laminar circuit 260 and the board-side surfacelaminar circuit 240 is omitted, or is replaced with an array of bondingstructures such as microbumps. In an illustrative example, the chip-sidesurface laminar circuit 260 may be replaced with an array of microbumpsor any other array of bonding structures.

The second solder material portions 290 attached to the fan-out bondingpads 928 of the fan-out package 900 may be disposed on the array of thechip-side bonding pads 268 of the package substrate 200. A reflowprocess may be performed to reflow the second solder material portions290, thereby inducing bonding between the fan-out package 900 and thepackage substrate 200. In one embodiment, the second solder materialportions 290 may include C4 solder balls, and the fan-out package 900may be attached to the package substrate 200 using an array of C4 solderballs.

Referring to FIG. 15 , a second underfill material portion 292 may beformed around the second solder material portions 290 by applying andshaping a second underfill material. The second underfill materialportion 292 may be formed around the second solder material portions 290by applying and shaping the second underfill material. The secondunderfill material portion 292 may be formed by injecting the secondunderfill material around the array of second solder material portions290 after the second solder material portions 290 are reflowed. Anyknown underfill material application method may be used, which may be,for example, the capillary underfill method, the molded underfillmethod, or the printed underfill method.

The second underfill material portion 292 may contact each of the secondsolder material portions 290 (which may be C4 solder balls or C2 soldercaps), and may contact vertical sidewalls of the fan-out package 900.The second underfill material portion is formed between theredistribution structure 920 and the package substrate 200. The secondunderfill material portion laterally surrounds, and contacts, the arrayof second solder material portions 290 and the fan-out package 900.

Optionally, a stabilization structure 294, such as a cap structure or aring structure, may be attached to the assembly of the fan-out package900 and the package substrate 200 to reduce deformation of the assemblyduring subsequent processing steps and/or during usage of the assembly.

Referring to FIG. 16 , a printed circuit board (PCB) 100 including a PCBsubstrate 110 and PCB bonding pads 180 may be provided. The PCB 100includes a printed circuitry (not shown) at least on one side of the PCBsubstrate 110. An array of solder joints 190 may be formed to bond thearray of board-side bonding pads 248 to the array of PCB bonding pads180. The solder joints 190 may be formed by disposing an array of solderballs between the array of board-side bonding pads 248 and the array ofPCB bonding pads 180, and by reflowing the array of solder balls. Anunderfill material portion 192 may be formed around the solder joints190 by applying and shaping an underfill material. The package substrate200 is attached to the PCB 100 through the array of solder joints 190.

Referring to FIG. 17 , a flowchart illustrates steps for forming anexemplary structure according to an embodiment of the presentdisclosure.

Referring step 1710 and FIGS. 1, 2A, and 2B, a redistribution structure920 including redistribution-side bonding structures 938 thereupon maybe provided.

Referring to step 1720 and FIGS. 3A-6 , a plurality of semiconductordies (700, 800) including a respective set of die-side bondingstructures (780, 880) may be provided.

Referring to step 1730 and FIGS. 3A-6 , the plurality of semiconductordies (700, 800) may be bonded to the redistribution structure 920 usingfirst solder material portions 940 that are bonded to a respectiveredistribution-side bonding structure 938 within a first subset of theredistribution-side bonding structures 938 and to a respective one ofthe die-side bonding structures (780, 880). A second subset of theredistribution-side bonding structures 938 (such as the dummyredistribution-side bonding structures 938D) is not bonded to any of theplurality of semiconductor dies (700, 800).

Referring to step 1740 and FIGS. 7A and 7B, a first underfill materialportion 950 may be formed around the first solder material portions 940,the redistribution-side bonding structures 938, and the die-side bondingstructures (780, 880).

Referring to all drawings and according to various embodiments of thepresent disclosure, a fan-out package is provided, which comprises: aredistribution structure 920 comprising a plurality of first metalbonding structures (such as redistribution-side bonding structures 938)on a side; a plurality of semiconductor dies (700, 800) comprising aplurality of second metal bonding structures (such as the die-sidebonding structures (780, 880)) that are attached to the first metalbonding structures 938 through bump portions (such as the first soldermaterial portions 940); and an underfill material portion (such as thefirst underfill material portion 950) laterally surrounding the firstmetal bonding structures 938 and the second metal bonding structures(780, 880) of the plurality of semiconductor dies (700, 800), wherein asubset of the first metal bonding structures 938 comprises at least onedummy metal bonding structure 938D that is surrounded by the underfillmaterial portion 950 and is electrically isolated from the semiconductordies (700, 800) and the second metal bonding structures (780, 880) bythe underfill material portion 950. Generally, the first metal bondingstructures and the second metal bonding structures may comprise any typeof bonding structures such as C4 bonding pads or C2 bonding pillars orany other type of metal structures to which a solder material can bebonded.

In one embodiment, at least one dummy metal bonding structure 938D islocated between a neighboring pair of semiconductor dies (700, 800)selected from the plurality of semiconductor dies (700, 800) in a planview. In one embodiment, the at least one dummy metal bonding structure938D does not have an areal overlap with any of the plurality ofsemiconductor dies (700, 800) in the plan view.

In one embodiment, the fan-out package comprises at least one dummy bumpportion (such as at least one dummy solder material portion 940D)located on a respective one of the at least one dummy metal bondingstructure 938D and not contacting any of the second metal bondingstructures (780, 880). In one embodiment, all surfaces of the at leastone dummy bump portion 938D are in contact with the underfill materialportion 950 or the at least one dummy metal bonding structure 938D.

In one embodiment, the at least one dummy bump portion 938D comprises atleast one row of dummy solder material portions 938D arranged along adirection that is parallel to, and is located between, a pair ofsidewalls of a neighboring pair of semiconductor dies (700, 800)selected from the plurality of semiconductor dies (700, 800). In oneembodiment, each of the at least one dummy bump portion 938D has a samematerial composition as the bump portions 938.

In one embodiment, the fan-out package 900 may include a moldingcompound die frame 910 laterally surrounding the plurality ofsemiconductor dies (700, 800) and comprising a molding compoundmaterial. In one embodiment, the molding compound die frame 910 mayinclude sidewalls that are vertically coincident with sidewalls of theredistribution structure 920.

In one embodiment, the redistribution structure 920 may include:redistribution wiring interconnects 924 embedded in redistributiondielectric layers 922 and electrically connected to a respective one ofthe redistribution-side bonding structures 938; and fan-out bonding pads928 located on an opposite side of the redistribution-side bondingstructures 938 and electrically connected to a respective one of theredistribution-side bonding structures 938.

In one embodiment, the plurality of semiconductor dies (700, 800) atleast one system-on-chip (SoC) die 700; and a memory die 800 such as ahigh bandwidth memory (HBM) die 810 including a vertical stack of staticrandom access memory (SRAM) dies (811, 812, 813, 814, 815) that areinterconnected to one another through microbumps 820 and may belaterally surrounded by an epoxy molding material enclosure frame 816.

According to an aspect of the present disclosure, a structure includinga fan-out package 900 may be provided, which may include: aredistribution structure 920 may include redistribution-side bondingstructures 938; a plurality of semiconductor dies (700, 800) which mayinclude a respective set of die-side bonding structures (780, 880) thatis attached to a respective subset of the redistribution-side bondingstructures 938 through a respective set of solder material portions 940;and an underfill material portion 950 laterally surrounding theredistribution-side bonding structures 938 and the die-side bondingstructures (780, 880) of the plurality of semiconductor dies (700, 800),wherein a subset of the redistribution-side bonding structures 938 (suchas the dummy redistribution-side bonding structures 938D) is not bondedto any of the die-side bonding structures (780, 880) of the plurality ofsemiconductor dies (700, 800) and is laterally surrounded by the firstunderfill material portion 950.

In one embodiment, the subset of the redistribution-side bondingstructures 938 (such as the dummy redistribution-side bonding structures938D) is located between a neighboring pair of semiconductor dies (700,800) selected from the plurality of semiconductor dies (700, 800) in aplan view. In one embodiment, the subset of the redistribution-sidebonding structures 938 (such as the dummy redistribution-side bondingstructures 938D) does not have an areal overlap with any of theplurality of semiconductor dies (700, 800) in the plan view.

In one embodiment, the fan-out package may include dummy solder materialportions 940D located on a respective redistribution-side bondingstructure 938 (such as a dummy redistribution-side bonding structure938D) selected from the subset of the redistribution-side bondingstructures 938. In some embodiments, the dummy solder material portions940D and the dummy redistribution-side bonding structures 938D may notcontact and/or be electrically connected to any of the plurality ofsemiconductor dies (700, 800).

In one embodiment, all surfaces of the dummy solder material portions940D may be in contact with the first underfill material portion 950 orthe subset of the redistribution-side bonding structures 938 (such asthe dummy redistribution-side bonding structures 938D). In oneembodiment, the dummy solder material portions 940D may include at leastone row of dummy solder material portions 940D arranged along adirection that is parallel to, and may be located between, a pair ofsidewalls of a neighboring pair of semiconductor dies (700, 800)selected from the plurality of semiconductor dies (700, 800). In oneembodiment, each of the dummy solder material portions 940D may have asame material composition as the sets of solder material portions 940.

According to an aspect of the present disclosure, a chip packagestructure is provided, which may include: a fan-out package 900including a redistribution structure 920 comprising redistribution-sidebonding structures 938, a plurality of semiconductor dies (700, 800) mayinclude a respective set of die-side bonding structures (780, 880) thatmay be attached to a respective subset of the redistribution-sidebonding structures 938 through a respective set of first solder materialportions 940, a first underfill material portion 950 laterallysurrounding the redistribution-side bonding structures 938 and thedie-side bonding structures (780, 880) of the plurality of semiconductordies (700, 800), wherein a subset of the redistribution-side bondingstructures 938 (such as the dummy redistribution-side bonding structures938D) may be located between a neighboring pair of semiconductor dies(700, 800) selected from the plurality of semiconductor dies (700, 800)in a plan view; and a package substrate 200 that is attached to thefan-out package 900 via an array of second solder material portions 290.

In one embodiment, the chip package structure may include a moldingcompound die frame 910 laterally surrounding the plurality ofsemiconductor dies (700, 800) and may include a molding compoundmaterial that contacts a peripheral portion of a planar surface of theredistribution structure 920.

In one embodiment, the chip package structure may include a secondunderfill material portion 292 laterally surrounding the array of secondsolder material portions 290 and the fan-out package 900.

In one embodiment, the subset of the redistribution-side bondingstructures 938 (such as the dummy redistribution-side bonding structures938) is not bonded to any of the die-side bonding structures (780, 880)of the plurality of semiconductor dies (700, 800), and may be laterallysurrounded by, and contacts, the first underfill material portion 950.

The various structures and methods of the present disclosure may be usedto provide a chip package structure including a fan-out package 900including dummy redistribution-side bonding structures 938D and dummysolder material portions 940D that modify the pattern of conduits for anunderfill material and increases the capillary force for the underfillmaterial. The various methods and structures of the present disclosuremay be used to reduce or eliminate voids in the first underfill materialportion 950 and to increase the reliability of the fan-out package 900.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A fan-out package, comprising: a redistributionstructure comprising a plurality of first metal bonding structures on aside; a plurality of semiconductor dies comprising a plurality of secondmetal bonding structures that are attached to the first metal bondingstructures through bump portions; and an underfill material portionlaterally surrounding the first metal bonding structures and the secondmetal bonding structures of the plurality of semiconductor dies, whereina subset of the first metal bonding structures comprises at least onedummy metal bonding structure that is surrounded by the underfillmaterial portion and is electrically isolated from the semiconductordies and the second metal bonding structures by the underfill materialportion.
 2. The fan-out package of claim 1, wherein the at least onedummy metal bonding structure is located between a neighboring pair ofsemiconductor dies selected from the plurality of semiconductor dies ina plan view.
 3. The fan-out package of claim 2, wherein the at least onedummy metal bonding structure does not have an areal overlap with any ofthe plurality of semiconductor dies in the plan view.
 4. The fan-outpackage of claim 1, further comprising at least one dummy bump portionlocated on a respective one of the at least one dummy metal bondingstructure and not contacting any of the second metal bonding structures.5. The fan-out package of claim 4, wherein all surfaces of the at leastone dummy bump portion are in contact with the underfill materialportion or the at least one dummy metal bonding structure.
 6. Thefan-out package of claim 4, wherein the at least one dummy bump portioncomprises at least one row of dummy solder material portions arrangedalong a direction that is parallel to, and is located between, a pair ofsidewalls of a neighboring pair of semiconductor dies selected from theplurality of semiconductor dies.
 7. The fan-out package of claim 4,wherein each of the at least one dummy bump portion has a same materialcomposition as the bump portions.
 8. The fan-out package of claim 1,further comprising a molding compound die frame laterally surroundingthe plurality of semiconductor dies and comprising a molding compoundmaterial.
 9. The fan-out package of claim 8, wherein the moldingcompound die frame comprises sidewalls that are vertically coincidentwith sidewalls of the redistribution structure.
 10. The fan-out packageof claim 1, wherein the redistribution structure comprises:redistribution wiring interconnects embedded in redistributiondielectric layers and electrically connected to a respective one of theredistribution-side bonding structures; and fan-out metal bondingstructures located on an opposite side of the redistribution-sidebonding structures and electrically connected to a respective one of theredistribution-side bonding structures.
 11. The fan-out package of claim1, wherein the plurality of semiconductor dies comprises: at least onesystem-on-chip (SoC) die; and a high bandwidth memory (HBM) dieincluding a vertical stack of static random access memory (SRAM) diesthat are interconnected to one another through microbumps and arelaterally surrounded by an epoxy molding material enclosure frame.
 12. Achip package structure, comprising: a fan-out package including aredistribution structure comprising redistribution-side bondingstructures, a plurality of semiconductor dies comprising a respectiveset of die-side bonding structures that is attached to a respectivesubset of the redistribution-side bonding structures through arespective set of first solder material portions, a first underfillmaterial portion laterally surrounding the redistribution-side bondingstructures and the die-side bonding structures of the plurality ofsemiconductor dies, wherein a subset of the redistribution-side bondingstructures is located between a neighboring pair of semiconductor diesselected from the plurality of semiconductor dies in a plan view; and apackage substrate that is attached to the fan-out package via an arrayof second solder material portions.
 13. The chip package structure ofclaim 12, further comprising a molding compound die frame laterallysurrounding the plurality of semiconductor dies and comprising a moldingcompound material that contacts a peripheral portion of a planar surfaceof the redistribution structure.
 14. The chip package structure of claim13, further comprising a second underfill material portion laterallysurrounding the array of second solder material portions and the fan-outpackage.
 15. The chip package structure of claim 12, wherein the subsetof the redistribution-side bonding structures is not bonded to any ofthe die-side bonding structures of the plurality of semiconductor dies,and is laterally surrounded by, and contacts, the first underfillmaterial portion.
 16. A method of forming a chip package structure,comprising: providing a redistribution structure includingredistribution-side bonding structures thereupon; providing a pluralityof semiconductor dies including a respective set of die-side bondingstructures; bonding the plurality of semiconductor dies to theredistribution structure using first solder material portions that arebonded to a respective redistribution-side bonding structure within afirst subset of the redistribution-side bonding structures and to arespective one of the die-side bonding structures, wherein a secondsubset of the redistribution-side bonding structures is not bonded toany of the plurality of semiconductor dies; and forming a firstunderfill material portion around the first solder material portions,the redistribution-side bonding structures, and the die-side bondingstructures.
 17. The method of claim 16, further comprising: forming thefirst solder material portions on the first subset of theredistribution-side bonding structures; and forming additional firstsolder material portions on the second subset of the redistribution-sidebonding structures, wherein the additional first solder materialportions are not bonded to any of the die-side bonding structures. 18.The method of claim 17, wherein the first underfill material portionlaterally surrounds, and contacts, each of the additional first soldermaterial portions.
 19. The method of claim 16, further comprisingforming a molding compound die frame around the plurality ofsemiconductor dies after formation of the first underfill materialportion.
 20. The method of claim 19, further comprising: attaching theredistribution structure to a package substrate using an array of secondsolder material portions; and forming a second underfill materialportion around the array of second solder material portions between theredistribution structure and the package substrate.